1. Field of the Invention
This invention relates to a sampling frequency converter for converting a sequence of input data samples having an input sampling frequency into a sequence of output data samples having a different output sampling frequency. The present invention finds particular use in, for example, converting between sampling frequencies associated with different PCM audio signal transmission systems.
2. Description of the Prior Art
Various PCM signal transmission systems have been introduced, many of these using different sampling frequencies to digitize and transmit audio signals. For example, the so-called compact disk system encodes an audio signal as a PCM signal recorded at a sampling frequency on the order of about 44.1kHz. As another example, a PCM processor is known in which an input audio signal is sampled at a frequency of 44.056kHz, this sampling frequency being used both to encode and decode a PCM audio signal. As yet another example, broadcast satellite systems are known to broadcast PCM audio signals in what has been designated the A mode at a sampling frequency of 32kHz and at what has been designated the B mode at a sampling frequency of 48kHz. Often, these different PCM samples having different sampling frequencies are to be interchanged such that the PCM signal produced by one system is to be transmitted over a communications system which uses a different PCM sampling frequency, and this signal is to be used eventually by yet another system employing a still different sampling frequency. Thus, the ability to convert PCM signals in particular, and sampled data in general, from one sampling frequency to another is desirable.
A relatively simple, straightforward sampling frequency converter relies upon digital-to-analog conversion of a PCM signal which, subsequently, is re-converted to yet another PCM signal at a desired sampling frequency. That is, the input PCM signal is converted to analog form and this converted signal then is sampled at the desired output sampling frequency in an analog-to-digital converter to derive the PCM signal with the desired output sampling frequency. Such DAC-ADC processing is relatively complicated and expensive and is subject to significant deterioration in signal quality. It should be appreciated that quantizing errors are introduced into each analog-to-digital conversion and these quantizing errors are cumulative when an input analog signal first is digitized, then converted to analog form and then re-digitized, all for the purpose of modifying the sampling frequency of the resultant PCM audio signal.
Digital converters by which an input PCM signal is converted to a digital signal of desired sampling frequency, without requiring an intermediate analog conversion step, are known. One example is shown in FIG. 1 of the appended drawings and this figure relates to a sampling frequency converter disclosed in Japanese laid-open Patent Publications Nos. 57-115015 and 61-204700. The prior art sampling frequency converter shown in FIG. 1 is supplied with an input sampling clock signal Fs.sub.(in) having an input sampling frequency fs.sub.(in) and with an output sampling clock Fs.sub.(out) having an output sampling frequency fs.sub.(out). A sequence of input data samples x.sub.i with the input sampling frequency fs.sub.(in) is converted to a sequence of output data samples y.sub.j having the output sampling frequency fs.sub.(out). A phase locked loop (PLL) 102 receives the input sampling clock signal supplied to a terminal 101 and multiplies the input sampling frequency fs.sub.(in) by a factor 2.sup.N (where, for example, N=7). As a result PLL 102 produces a high frequency clock signal of a frequency 2.sup.N.fs.sub.(in). This high frequency clock signal is supplied to a counter 103 which is set in response to each pulse of the input sampling clock signal Fs.sub.(in) and is reset in response to each output sampling clock signal Fs.sub.(out). The output sampling clock signal is supplied to the reset input R of counter 103 and also to a latch input L of a N-bit register 105. The output of counter 103 also is coupled to register 105; and the count reached by the counter is transferred to and latched in the register upon the occurrence of an output sampling clock pulse.
As a result, the count reached by counter 103 and latched in register 105 is representative of the phase of the output sampling clock pulse with respect to the immediately preceding input sampling clock pulse. That is, the phase difference between the output sampling point and the immediately preceding input sampling point is represented by the N-bit count which is normalized to unity. This N-bit normalized phase difference is supplied to a calculating circuit 106.
Calculating circuit 106 functions to convert the input data samples x.sub.i to output data samples y.sub.j in response to each N-bit normalized phase difference supplied thereto by register 105. The converted output data samples are obtained at output terminal 108.
The relationship between the N-bit phase data stored in register 105 and represented as phase data .phi..sub.j, input data samples x.sub.i and output data samples y.sub.j are graphically depicted in FIG. 2. Of course, if the input data samples are converted to analog form, the resultant analog signal would, ideally, be identical to the analog representation of output data sample y.sub.j. Calculating circuit 106 functions to calculate the sample value of an output data sample y.sub.j at an output sampling point in response to an input data sample x.sub.i by using multinomial interpolation or digital filtering, as described below.
As an example, and with reference to FIG. 3, the method of calculating an approximate value of an output data sample by multinomial interpolation is represented. Here, the multinomial interpolation is interpolation of the first degree, commonly referred to as linear interpolation. From FIG. 3, it is seen that samples x.sub.i and x.sub.i-1 represent amplitudes of the input data samples, y.sub.j represents an amplitude of a data output sample, and .phi..sub.j represents the phase of an output sample point relative to the inmediately preceding input sample point (0.ltoreq..phi..sub.j &lt;1). The amplitude of y.sub.j of the output sample point may be expressed as: EQU y.sub.j =x.sub.i-1 +(x.sub.i -x.sub.i-1). .phi..sub.j.
Thus, the output amplitude at a desired output sample point may be calculated from the data input amplitudes x.sub.i and x.sub.i-1 and from the phase data .phi..sub.j.
An example of digital filtering is represented by the waveforms shown in FIG. 4. Here, the input-to-output sampling frequency conversion ratio is assumed to be L/M, wherein L and M are integers. Sampling frequency conversion is carried out as follows:
First, L-1 zero-valued samples are filled between adjacent samples of the input sampling sequence x.sub.i. As a consequence of such processing, the apparent sampling frequency is increased by a factor of L but the spectrum of the input sampling sequence remains unchanged. The sampling sequence with this increased sampling frequency then is convolved with (or multiplied by) a coefficient sequence K.sub.0, K.sub.1, K.sub.2, . . . , K.sub.r, . . . , K.sub.2r-1, K.sub.2r which are samples of the impulse response of a low-pass filter having a pass band which passes the lower of the input sampling frequency fs.sub.(in) or the output sampling frequency fs.sub.(out) in a range up to L/2 times the passed sampling frequency. As a result of this multiplication processing, interpolated sample data having a sampling rate L times that of the input sampling frequency is obtained.
The interpolated sample data y.sub.j ' whose sampling rate is L times the input rate may be represented as: ##EQU1## In order to calculate the amplitude of one output sample, the Lth coefficients may be extracted and summed in a summation of products process that may be carried out by a digital signal processor (DSP) Then, the amplitude of the L-th output sample may be reduced by a factor 1/M, to produce an output data sample y.sub.j whose sampling frequency is converted to L/M relative to the input sampling frequency. By performing the foregoing calculation for each output sample point once for each M input data samples, the number of calculations can be reduced by the factor 1/M.
Obtaining the output sampling sequence y.sub.j by the aforementioned convolution calculation generally relies upon a high speed clock signal which is generated by increasing the input sampling frequency (or the output sampling frequency) many times. This multiple of the input data sampling frequency (or output data sampling frequency) is used to drive the digital signal processor.
Another prior art example of a sampling frequency converter is illustrated in FIGS. 5-7 In this example, the input data sequence is over-sampled by a fixed ratio, for example by a factor of 4, and the oversampled input data sequence is supplied to a buffer circuit from which four data samples are read, each being multiplied by a coefficient related to the phase difference between the input sampling clock Fs1 and the output sampling clock Fs2. The products are summed, thereby producing the desired output data sequence at the selected output sampling frequency, with the resultant output samples each exhibiting proper amplitude values.
As shown in FIG. 5, input data having an input sampling rate of fs.sub.1 is supplied to a two-stage fixed ratio over-sampling filter 1 and is converted into data whose sampling frequency is a multiple of the input sampling rate. The first stage of over-sampling filter 1 operates to increase the input sampling frequency by K.sub.1 -times and, thus, may be considered a K.sub.1 -times over-sampling filter. Likewise, the second stage of filter 1 functions to increase the sampling rate of the samples supplied thereto from the first stage by a factor K.sub.2. Hence, the second stage of filter 1 may be considered a K.sub.2 -times over-sampling filter. In a typical embodiment, K.sub.1 =K.sub.2 =2, resulting in an increase in the input sample rate by a factor of 4. The output of over-sampling filter 1 is supplied to buffer 3. Within a period Ts1 of the input sampling clock Fs1, there are included four samples of the oversampled input data, and these four samples are read out from buffer 3 during the period Ts1. The buffer write-in and read-out operations are controlled by an output of clock processor 4.
The four samples read from buffer 3 are multiplied by predetermined coefficients in a digital filter 2, the latter also being controlled by clock processor 4. As a result of this multiplication operation, output data samples having the desired sampling rate Fs2 are obtained.
The instantaneous relative time difference dt.sub.i between the input sampling clock Fs1 and the output sampling clock Fs2, that is, between the input and output data samples, is detected by clock processor 4. Based upon this relative time difference dt.sub.i, buffer 3 and digital filter 2 are controlled in the manner described below.
FIG. 6 is a waveform diagram useful in understanding the operation of digital filter 2. In FIG. 6, the oversampled input data samples are represented as samples x.sub.i, x.sub.i+1, . . . , having a sampling rate 4fs1; and output data samples y.sub.i-1, y.sub.i, . . . , exhibit the sampling rate of Fs2 and are produced at times relative to the oversampled samples x.sub.i, x.sub.i+1, etc. The amplitude of an output sample y.sub.i is obtained by multiplying four oversampled samples x.sub.i+3, x.sub.i+4, x.sub.i+5 and x.sub.i+6 by coefficients c.sub.i, c.sub.j, c.sub.k and c.sub.l, respectively, and then adding all of these products together. The coefficients c.sub.i, c.sub.j, etc. are samples of the impulse response of a low pass filter, similar to that shown in FIG. 4, represented by, for example, 32K samples. These coefficient samples are stored in a coefficient table C which is shifted so that its center coincides with the time at which output sample y.sub.i is produced Then, the coefficients c.sub.i, c.sub.j, c.sub.k and c.sub.l are selected from the coefficient table C at the times that oversampled data samples x.sub.i+3, x.sub.i+4, etc. are read from buffer 3.
The relative time difference dt between an input data sample, assumed to be sample x.sub.i+3, and output sample y.sub.i (the precise position where an output sample amplitude is to be calculated) cannot be measured accurately due to clock jitter or the like. A time-related error in determining the position of the output sample causes an amplitude error in the sample amplitude calculation. This amplitude error must be kept below one quantizing step. That is, the least significant bit in an output sample cannot be erroneous. Since the relative time difference dt cannot be measured, it must be calculated to an accuracy of virtually 16 bits.
FIG. 7 is a block diagram of one prior art example of clock processor 4 used to provide an error-free updating of relative time difference dt(i) carried out by measuring and averaging the output sampling period Ts2 and accumulating relative time differences dt. The embodiment of FIG. 7 includes a phase locked loop circuit 5, a counter 6, a random access memory (RAM) 7, adders 8 and 9 and delay circuits 10 and 11. Phase locked loop 5 generates a clock signal whose frequency is a multiple of the input sampling frequency fs1, that is, a clock frequency equal to 2.sup.k fs1. This clock signal is used to measure the period Ts2 of the output sampling frequency fs2. This measured period is designated Ts2q(i) which is coarsely quantized with an accuracy of 6 to 7 bits. The measured output sampling period Ts2q(i) is averaged over a sufficiently long time period to increase its resolution to 16 bits (or more), and this averaged output sampling period is designated Ts2(est)(i). The average value Ts2(est)(i) must be measured such that no systematic down-rounding or up-rounding occurs over several samples because values due to such up-rounding or down-rounding accumulate as errors. To obtain the average value of clock period Ts2, a simple FIR averaging circuit, for example, one with a z-Transform EQU H(z)=(1-z.sup.-n)/(1-z.sup.-1)
can be used. One advantage to such FIR averaging circuits is that they introduce no quantization error. In FIG. 7, RAM 7, adder 8 and delay circuit 10 function as averaging circuitry, and the value Ts2(est)(i) is provided at the output of adder 8.
When starting from an arbitrary or defined initial value dt(0), the relative time difference dt between input and output data samples is updated as EQU dt(i+1)=[dt(i)+Ts2(est)(i)]Mod(Ts1).
With numerical values normalized to a unit of Ts1 =1, the modulo operation requires no additional hardware.
In the aforedescribed prior art examples, calculation and control of the output data samples are carried out as a function of the relative time difference dt.sub.i, and this relative time difference dt.sub.i is determined from the input sampling clock Fs1 and the output sampling clock Fs2. That is, once the time difference dt.sub.i is calculated, it is used to generate the addresses for the filter coefficients which, in turn, are used to multiply the oversampled input data samples to calculate the output data samples. This technique suffers from several disadvantages: the overall calculating process is complex and time-consuming. Also, since the read/write operations of the buffer have been controlled as a function of the time difference dt.sub.i produced by clock processor 4 (FIG. 5), such read/write control has been complicated.